Hm, how did you get the number of Logic cells without having a qpf and qsf file?
Why do you design a control logic with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).
I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.
While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me
. So you should recalculate your expectations with the number of 1925 LEs per hasher.
Why do you design a control logic with 288 IOs for a chip with only 167 usable IO pins (153 usable on the DE0 (including th pins for RAM etc.).
I tried to test compile the design for a cyclone IV with 30 kLE but fiting failed due to lack of IO pins but the device usage was 88% which makes it not so certain (to me) that you could squeeze 19 hasher in the 22 k device.
While checking the numbers, i could verify that a hasher stage 'miningcore' would use 1157 LEs but this number excludes the sha256core submodule which seems a very important part to me
. So you should recalculate your expectations with the number of 1925 LEs per hasher.Correction: the .zip file comes with only a quickly thrown together sdc and no qpf, just vhdl.
-Edit-
I can admit a mistake, you're right, with zero register duplication, no optimization, no resource sharing, etc, the core takes up 1925. But let me be very clear: with optimizations that size goes down significantly, I've shut off all optimization in order to preserve logic that would otherwise be synthesized away. To think that it won't use sharing with all of the XOR, AND, and + repetitions is absurd.
Apparently, however, I need to revamp my numbers, so I'll get something back to you on the core controller soon.
Also, in the design report the multiplexer restructure savings alone are 81 LEs, so 1925 -> 1844 for the current design.
In better news, I have my mining core shrunk from 768 -> 582 LEs as of today.
Interesting. Assuming your design can be ported from the Cyclone IV to the Stratix III, an EP3SL200 at 213MHz with 250 of your 800-LE cores would produce 416 Mhash/s. That would account exactly for the performance of the BitForce Single (rumored to be two EP3SL200 chips = 832 Mhash/s)...
Does it port? Yes. I don't have experience with the Stratix III series, does it use the same architecture (or similar) to that of the Stratix IV? If so the logic count would be decreased (compiling this on my Stratix IV gave me better numbers than the ones I've quoted). I haven't looked into the pricing on that unit but work will continue and if Altera devices become advantageous, then we'll use them.