Quote from: cedivad on September 21, 2014, 10:11:18 PM

Quote from: aerobatic on September 21, 2014, 08:09:08 PM

late 2015 will probably be closing in on 0.1 J/GH.

How? Is CT's 16nm design, when downclocked, 3 times more efficient? I doubt that. So how is someone gonna archive 0.1J/GH on 16nm within one year?

I personally think that it will be easier to optimise farm locations, rather than hardware from say 0.25J/GH to 0.15J/GH.

i think anything that says 'x' times more efficient isn't the full picture.

i think that the industrial scale bitcoin mining industry is already homing in on the cheaper places to host... iceland, eastern washington, etc... already thats where much of the world's mining is moving to and its only going to get more concentrated.

so... once everyone is pretty much hosting for a similar price... the ONLY thing you can do is design a better chip.

So what IS a better chip?

well, for one... the chip has to be optimised for something... in the previous asic generation of oh so long ago (2013 ;-) most of the asics were optimised for performance. it was the max performance possible. designers would 'throw silicon' to make it go faster.

'Performance' has been easy to sell to customers, so it was easy to justify. any design that gives more gigahashes per retail dollar is worth doing, because the retail market cares only about the headline number - How many gigahashes is it? the retail market isn't so astute as to worry about the other (potentially more important) factors.

the retail market hasn't, as yet, figured out that the cost of hosting over the year is becoming very critical and probably more important than the cost of purchasing... and that its a TCO - Total Cost of Ownership that matters most. Combining what the system costs to buy, PLUS what it costs to operate together to consider its total running cost over a period of, say, a year.

Its for this reason that cloud hashing becomes more attractive because in many cases its an 'all in' cost. Especially when some people (like Cointerra's and Cloudhashing's) cloud offerings which includes a year of running costs in the purchase price... whereas some other cloud hashing companies (like cex.io) hide the running costs in the fine print and deduct them each month from the mined revenue. If you factor in the running costs of those guys for 12 months their offering looks altogether different and considerably more expensive.

but the model for mining has recently changed... now that its borderline profitable (with present generation systems at circa 1W/GH)... the attention has been turned far more than ever before towards lower power designs.

there's two types of asic designers around right now. one type, makes asics that are the lowest cost GH's (these are mostly chinese companies). They don't seem to know how to make the chips low power, and they don't seem to care. their goal is to make them as low cost as possible, regardless of the power consumption. And there appears to still be a retail market for this type of asic company. Since these guys make their money selling systems, they probably won't care about the on-going operational cost of their gear and they will focus their sales on people who either don't pay for their own electricity (students?) or people who are too naive to realise they should be worrying about it.

then there's the other group of asic designers... the ones that care about the power consumption and are making decisions focussed on lowering the on-going operational costs of the silicon. Its these guys - who usually operate their own datacenter as well as sell to wholesale/retail buyers.

this time around, some asic designers are 'throwing silicon' at making it low power. but throwing silicon around something that the retail market has usually ignored is risky and the lower power designs will be more appealing to the professional or industrial scale miners, because they actually DO care how much it costs to run, whereas home miners tend to ignore the cost of power and especially the cost of cooling.

The ways to get lower power asics are simple. Better designs, more optimised... running at lower voltages... and moving to smaller geometries... and doing more custom cells or even full custom.

BitFury has chosen to go the full custom route in the past.. and its a slow route. slow but sure. doing full custom asics are extremely time consuming... they take months and sometimes years. AND, there's a risk that it doesn't work when you get your silicon back... because a full custom design would ideally need to be tested with engineering samples and this yet again can add months to the design process... however, they hinted in their recent press release that they're designing a different architecture in the future that will allow them to more rapidly migrate to smaller geometries. These hints suggest they're no longer going the full custom route and are instead utilising standard cell with some customised cells - and not full custom any longer). This is a similar strategy to Spondoolies.

The fastest way to get the next generation 'lower power' and 'lower cost' asics is to utilise the best and newest possible geometry. This is the Cointerra strategy. They're first on 16nm and that will give them an advantage of lower power and lower cost and the ability to benefit more directly from Moore's Law. The other guys who are still on previous 20 and 28nm processes will probably also achieve their lower power chips in due course, but not as quickly as migrating their designs onto the next geometry because they will need to design considerable parts of their chips in custom cells (time consuming). But the two strategies aren't incompatible and in fact there's no reason why Cointerra too couldnt also do a full or semi custom design for their next one in parallel. Its a tried and tested strategy that Intel uses for their microprocessors. They call it Tick Tock. The Tick is each time they go onto a new geometry they end up with a faster and lower power chip... and the Tock is the extra time they need to make it full custom and more optimised architectural improvements for that geometry. They have parallel teams doing this. http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html

edit: to answer your question more directly. You need to do two spins of a chip in the same geometry to make it the most efficient. Like Intel. Spondoolies is pursuing right now. They just released RockerBox on 28nm, and now they're working on PickAxe on 28nm. They're both 28nm, but the latter one has a lot more optimisations in it.. Cointerra is doing a similar thing, only in 16nm. The first one, ct has announced early 2015 delivery... could be one of the first asics on 16nm in bitcoin land, and thus will take advantage of the lower power and higher performance that this geometry will bring. And the 2nd asic - potentially in late 2015, will be a newer version with architectural improvements and customisations to better optimise for the new geometry. This Tick Tock strategy has served Intel well for a couple of decades and it will work for Spondoolies and Cointerra as well.