Quote from: aTg on February 05, 2013, 01:46:59 PM

Each chip has about 280MH / s, this means that they are a hardcopy of a FPGA and not a full custom ASIC.

This "hardcopy" comment is just misinformation.

Various FPGA copy processes need to be ordered through the respective intelectual property owner, eg.

HardCopy through Altera
EasyPath through Xilinx
etc.

In case of Avalon if this was an FPGA copy they would place an order with Xilinx not with TSMC.

It clearly is a custom ASIC.

Now the adjective "full" has no well-defined meaning next to "custom ASIC". By my reading of the posts in this forum only two ~~persons~~ creatures are working on a full custom ASIC: bitfury and ~~yohan~~ yohan's cat.

Quote from: yohan on May 19, 2012, 06:37:08 PM

The designer is watching.

The distinctive mark of a full custom designer is that his simulation result errors are narrower than the manufacturing process variance. The way I interpret the words "full custom" would mean that the designer had run an analog level simulation on BSIM (or an equivalent toolset). The error-bounds on such simulations are very narrow, in fact the proper simulation would consist of multiple simulation runs modeling various corners of the manufacturing process. This is just time consuming.

It is of course possible that some vendor really does full custom design, but deliberately spreads misinformation on this forum to hide their intellectual property.

It is also possible that some vendor is in a posession of some EDA tool that they don't have a full license and/or don't fully understand how to operate and/or don't have all the required input data for models. This would be another explanation of unusually wide error bounds on simulation.