According to the Xilinx docs SSO's *does* influence internal logic / other components (especially the MCB).
Er, I agree that this is
true, but I haven't been able to find anywhere that Xilinx actually
admits this for all-fabric (no I/O) designs. Have you found any place where Xilinx admits that excessive switching of fabric (not
outputs) can cause fabric (not output) errors?
That's the frustrating part. Clearly the device is not operating the way XPA predicts, and the the XPA results are effectively part of the datasheet. Or maybe I'm just spoiled by StarRC.