It helps but logic/RTL verification is one of the easiest steps in a modern ASIC design.
You derisk that by using - guess what - FPGAs. The lower level physical/analog design
is what fucks over most amateur ASIC designs.
-rph
I see, so the person or company that is designing an ASIC really is responsible for the entire thing, it isn't as simple as handing some completed HDL over to a company who will then interpret them into their process and print some chips.