Post
Topic
Board Securities
Re: ASICMINER: Entering the Future of ASIC Mining by Inventing It
by
rudi
on 10/12/2014, 09:07:07 UTC
Shouldn't we all be super stoked right now?

We produced the test boards in December 2nd, and got the packaged sample chips last night.
We were busy testing since then and had some preliminary data already.

Technology: TSMC 28nm HPC

Package: FCLGA 5mm x 5mm

On chip efficiency:
    0.56V | 4.8GH/s | 1.95A | 0.2275W/G
    0.60V | 5.2GH/s | 2.14A | 0.2469W/G

We are still testing more voltage-frequency combinations, as well as more chips.
But the test results are stable and solid so far.

Our power solution evolved from Prisma allows very low overhead in supplying very
low voltage levels to chips compared to standard DC/DC converters. Therefore on-wall
power consumption would be very close to (our on-chip power/PSU efficiency).

After the thorough testing of single chip boards, we are going to test boards with chained chips.