Globalfoundries 10nm ASICs?

Sorry, no way! GF has 28/22/14/12/7nm. There is no 10nm node at all!

I fully agree. The more useful information was, that they “talk” about 7nm with TMSC. This technology will be more likely the base for the S11 ASIC than 12nm.
So the good news is, it seems that they didn’t even start the 7nm design process.

I’m pretty sure, that Halong didn’t design and implement a 10nm ASIC without help. Design teams capable of 10nm implementations are not coming out of nowhere.

In principle Innosilicon is a design service company. They are realizing any kind of microchips for any customer who is paying them. Normally that kind of service companies are “pure-play design service”, which means that they are not releasing products labelled with their company name. Innosilicon seems not to be so strict here, they have own products too.

However, I guess that Halong contracted/paid Innosilicon to implement their 10nm ASIC as a turnkey service. Halong covered the complete NRE costs, took all the risks and is the owner of the resulting ASIC design and mask-set. The engineering was done by Inno (maybe Halong developed the ASIC architecture and parts of the front-end design).
That is the way it goes, nothing really wrong here.

A professional marketing guy? No, I’m not that kind of professional. 

It always takes me a while to extract the useful information from your posts, but believe me, I finally agree with you, sometimes.
 
Yes, having the ability to switch ASICboost on/off (as Bitmain did), give you a chance to compare the two modes. It would even be possible to do a complete power shut-off of the unused backup logic in ASICboost mode, to avoid the leakage of these logic parts. But it still consumes silicon area, which increases your production costs in terms of $/GH.

Halong has chosen a very aggressive way to implement ASICboost without any backup logic for a non-ASICboost mode. In this way they have enabled the full potential of ASICboost in terms of J/GH and $/GH. I wouldn’t dare something like that, without the support of parts of the community (e.g. Slush). The risk of falling down to only 25% of the maximum performance would be much to high, in case no pool would support rolling versions.
So yes, I agree, it was “a sort of political compromise or attack/defense strategy”.

These numbers are not based on completely ideal assumptions. They are based on the fact that the part of the pipeline, which outputs could be reused by other cores, counts for about 25% of the overall core logic of a single core.

Ok, you are right, the FO/load cap of the reused bits is increased by feeding multiple cores. But the reused outputs are only 32 bits in contrast to a 512 bit wide pipeline without increased FO, implemented only once.

So the gain of an ASICboost duo-core in terms of power efficiency will be a bit less than 12.5%, but not much.

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Moderator's note: This post was edited by frodocooper to remove a nested quote.

Please have a look at page 8 of the original ASICboost white paper:
https://arxiv.org/ftp/arxiv/papers/1604/1604.00575.pdf

There is a Duo-Core ASICboost implementation shown. In case you would operate such a Duo-Core in a non-ASICboost mode (at the same clock frequency), you would run at 50% of the ASICboost performance, because only one of the two cores can operate in non-ASICboost mode.

Ck said in another thread, that the Halong miner is at 25% of its performance in a non-ASICboost mode. Because of that I would assume, that they implemented a Quad-Core, which requires about 18.75% less silicon area (leakage power)/logic toggling (dynamic power) compared to 4 non-ASICboost cores.

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Moderator's note: This post was edited by frodocooper to trim the quote from NODEhaven.

When TSMC is talking about “high performance” they have e.g. GPUs in mind. NVIDIA and former ATI (now AMD) are TSMC customers. There are lots of high performance networking product e.g. from Broadcom or Qualcom too.
In principle it is everything, which is not battery powered and needs maximum compute performance.

No offence, but NotFuzzy is right.
If you want to build everything, which is currently mining again, from scratch, you would have to produce less than 60k 28nm wafers (assuming about 100 THash/s per 300mm wafer).
This is the monthly production capacity of a single giga fab. TSMC, GF, Samsung, Intel, UMC, … all the major foundries have at least one 28nm giga fab. There are not so much 14/16nm fabs around, but considering Moore’s law only 30k 14/16nm wafers would be needed in this case.
The theoretical revenue a foundry could make, if it produces all ASICs for 6 Exa-Hash/s in 28nm (or 14/16nm) would be less than $300M. That is about 1% of TSMC’s yearly revenue. I’m not saying, that this is nothing, it’s much more than I was predicting 3 years ago. But it’s probably still not enough to get any special conditions for early access to the currently very rare 7nm production capacities.

Timo Hanke’s asicboost paper explains the benefits and hardware prerequisites quite well. If I understood it right, there is no need for changing the Bitcoin protocol to enable it, it just has to be designed in the ASIC and one would need a custom miner software. So in theory all S9 could already run with asicboost and nobody would know.
But the paper also shows, that if you want the full asicboost potential in terms of silicon area and energy efficiency, the resulting ASIC could only be used with asicboost.

So if Segwit would prohibit asicboost (I don’t know if this is really the case), these kind of ASICs would be garbage.

I also guess that if somebody implemented asicboost in their ASIC (most likely anybody with <0.10 J/GH ) they probably added a kind of a “legacy” mode, which would enable a classic operation mode again, in case that somebody changes the protocol. This would cost silicon area, but still saves a lot of power.
But maybe they were just too greedy to add this backup solution.

If that is the final truth , also Qualcomm and Mediatek would not go for 10nm so early for their smartphone processors. They are doing this because they are expecting more performance and better efficiency (longer battery run time) at lower production costs (ideally). This drives the semiconductor industry since 50 years.

You will get for sure higher performance and better efficiency at 10nm compared to 16nm. But that the production costs are reduced in parallel is very questionable. This good old Moore's Law effect disappeared already at the 28nm to 16nm transition.
I bet, that Bitmain pays more for the pure 16nm silicon than they did for 28nm normalized to a TH/s.
And a Bitcoin ASIC is much more sensitive to production costs than a smartphone processor, especially if you have free or almost free power.

10nm is not so far!

TSMC and Samsung already did several 10nm tape-outs (e.g. smartphone processors of Qualcomm and Mediatek). These kind of technology will be pretty sure part of the next gen smartphones in 2017.

Globalfoundries bought IBM's microelectronic manufacturing business completely in 2015. GF/IBM skips 10nm and goes directly to 7nm, but there will be for sure no 7nm products in 2017.

Last potential foundry player (in this league) is Intel. They are probably ahead of TSMC and Samsung, but very picky with respect of selecting customers.

Meanwhile Bitmain is a “midsize” TSMC customer. If they want, they probably can get a 10nm production slot. But why should they invest another $10M NRE if nobody is challenging them at 16nm?
Anyway I'm sure that Bitmain has already access to the TSMC 10nm technology and is designing the next gen ASIC. So they will go into production as soon as they need to.

Do you mean, that the S9 is using the patent-pending ASIC boost method?

Anybody with inside knowledge?

Just curious, what went wrong with the 0.06 J/GH 16nm Solar ASIC?
They claimed to have it since when? Beginning of 2015?

How can a company with this piece of “alien” hardware loose the mining competition?

Even if Bitfury delivers its 16nm ASIC in about 2 weeks , the Solar ASIC would still be more efficient!
And even including Swedish energy taxes they should have <$0.06/kWh power costs in northern Sweden!

Was this Solar ASIC just FUD?
Was KNC not able to create a working miner based on it?
Or is the ASIC too expensive caused by low 16nm yield?

Hey Hey! I dug up the press release!

Not long time ago a foundry guy told me that he thinks that it is the wrong way for a foundry to hunt for the big $500M opportunities only. He said, the foundries have to take the “small” $50M opportunities seriously in the future.

The sad thing is, that $50M in 28nm wafers would be about 1000 PH!

Perfect would be one, which is in your neighbourhood or at least in the same time zone.

Sorry, I don't know any IC design service companies in Minnesota.

www.uniquify.com
(did the design for Hastfast)
www.open-silicon.com
(did the design for Cointerra)

Both are located in CA. Probably not the best examples looking at how the stories ended.

Another one in US (also CA) is www.esilicon.com

But in principle I doubt that any of these companies would implement a 0.1 J/GH ASIC for you below $1M for design services (this does not include the mask costs), if they are interested at all.

The reason for this is that there are no low hanging fruits anymore. If you want to be successful with a new BTC ASIC, many custom CAD monkeys have to work really hard, because any competitive ASIC has to be implemented based on custom digital design techniques to reach 0.1 J/GH.
It is easier to reach this target based on 16nm, but probably not impossible in 28/22/20nm. Anyway it would require very high effort, compared to the first ASICs which hit the market in 2013.


You can do nothing with bare die samples, despite you have suitable test prober equipment, which is also not cheap.

Maybe a comprise would be a COB setup (Chip on Board). Here the bare dies are directly wire bonded on a fine pitch PCB.

Don't worry, I don't take this personally. The more posts from 2112 I read, the more I get the feeling that he is probably a little bit too long out of the real world ASIC business and if he ever got to know it, then more from an academic point of view. By the way, he is not the only one who had strange experiences with Apache (now Ansys) tools and these are only niche tools, which you need for a very small part of the overall design flow (sorry for the CAD monkey terms ).

You have of course to do a design exploration of different variants of hashing cores. And if you want a complete picture then you have to do it in different technologies. But I doubt that you have to tape-out all these variants to get to know, which one is the best and should be used in the final ASIC. If you are an experienced CAD monkey you can determine which of your variants is the best with high confidence without silicon, at least relatively to each other. Real silicon results will be +/- 15%, maybe +/- 20%, but not more, otherwise you missed something very important during the design phase.
And in any case, finally every working mining ASIC will be a layout based on a replicated highly optimized hashing core, because there is no other efficient way to implement so called multi/many core systems.

If I would do a prototyping run like discussed above (based on a MPW run), then I would try to get as close as possible to the final ASIC with respect to performance, die size and packaging concept to be able to pipe clean the complete miner system design including cooling setup, string regulation concept and so on. That does not exclude that you include different variants of hash cores in the prototype.

Anyway you should keep in mind, that the complete prototyping cycle AFTER you have finished the design will take at least 6 months including packaging, measurements and analysis. That is why almost everybody who has “successfully” brought a miner to market skipped this step.

Yes, bare silicon dies in gel-pak.

But if you go for a standard package, prototype packaging service is also available:
http://www.europractice-ic.com/prototyping_packaging.php

Don't be scared, in volume production the packaging per sample is much cheaper.


Yes, but this is not much for a mining ASIC even in 22nm. I guess it should equate to about 10 ... 15 unrolled hash cores, because this 22nm GF node is only a 80% shrink of the GF 28nm node, not a true 50% shrink like other 20nm nodes. But therefore the 22nm masks cost only a little bit more than a 28nm mask set.


You have the choice

www.synopsys.com
www.cadence.com
www.mentor.com

You need a bunch of these tools and people, who know how to use them.

In general EDA tools for advanced nodes are very expensive ("big problem, small market"). A complete full+semi custom tool-set for a small design team will cost you at least $500k per year.
And yes, Universities have these tools almost for free, but for strictly non-commercial use. As soon as you want to design something, which could be commercialized directly or indirectly it is illegal to use University licenses for it. If something like this would be discovered by the EDA vendors, you and the University would have huge problem.


If you like to get your feeds in the water here, it would be better to cooperate with a IC design service company at least for the first project. You bring the chip concept and architecture, they help you to design, manufacture, package and test it.
From my point of view, it is almost impossible to build up the required competences from scratch, despite you hire some experienced IC designers in your company.
Where is your company located?

Just to be clear. This means you don't have any information which confirms your statement "[sample chips] (which had already been sent to big players, but not us)"?
It is just an assumption of you without prove?

Did one of the "big players" confirm that he received samples to you personally?
Or are this just rumours?

Just to be sure that I got you right. You are talking about a S7 based 10MW setup with less than $40/kW per month hosting costs? About 8500 S7?

What is the S7 equivalent equipment you are talking about?

Could you please send me the contact to the Islandic datacentre, which offers $40/kW all inclusive?
If this is true, you got an extremely good deal!

Is this an existing operation or something you or somebody else is planning?

I guess it exists and you would either like to buy or sell it. Therefor you want to know what it is worth?

From my point of view this is one of the most competitive mines one can currently operate (forget about all this China free MW myths! ).
So you would be one of the last miners standing and should be able to mine with a profit for at least 12 months. Even after the halving and when the next gen 16nm miners hit the market.
So I would pay 50% of the conservative estimated mining profit of the next 12 months.