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Showing 16 of 16 results by LazarusLong
I was working on a port with libftdi to replace the d2xx lib - it did not work, some bits in the data streams differ.
Great work! I really need this stuff on openwrt...
Great work! I really need this stuff on openwrt...
Hi,
My board is back!
I changed to 12V connector and it works. On the 5 V molex which I used before no current gets pulled at all. Seems you are right, the fuse is gone. Don't know how this could have happend. I am using a standard PC power supply....
Maybee under 5V voltage drop? The current gets higher if the voltage drops and fuses are likely to burn?
Can you give me the position and data of the fuse? I can relace it by myself - less hassle comparing to sending the board back and forward through the customs...
Is it the part with the "w" on it?
My board is back!
I changed to 12V connector and it works. On the 5 V molex which I used before no current gets pulled at all. Seems you are right, the fuse is gone. Don't know how this could have happend. I am using a standard PC power supply....
Maybee under 5V voltage drop? The current gets higher if the voltage drops and fuses are likely to burn?
Can you give me the position and data of the fuse? I can relace it by myself - less hassle comparing to sending the board back and forward through the customs...
Is it the part with the "w" on it?
It sounds to me like you had a good system going, and I doubt your FPGAs are dead. Do you have a volt-meter that you could measure the output from your power supply with? If that looks good, it could be that the protection fuse on X6500 has blown. This fuse should only blow as a last resort, particularly if you supplied reverse voltage, so I don't know why it would blow in your case. Were you using the Molex connector or barrel connector? Each power input has it's own fuse so you could try using the other one (if you have a suitable supply) to figure out if the fuse is to blame. If it is, please send it back and I'll replace the fuse for free.
If you don't feel comfortable testing it, I'll gladly diagnose it for you if you send it back. If you're pretty handy, you could replace the fuse yourself or bypass it entirely (although you'll lose the protection it provided, of course). I'll email you the address to ship it to.
Sorry for the trouble!
If you don't feel comfortable testing it, I'll gladly diagnose it for you if you send it back. If you're pretty handy, you could replace the fuse yourself or bypass it entirely (although you'll lose the protection it provided, of course). I'll email you the address to ship it to.
Sorry for the trouble!
Hi,
Was running the 180MHz file for about 30 seconds, then the miner aborted with IO errors after some succesful hashes.
I did a complete reset but the board does not come back
I had two 40mm fans above each heatsink, the did not get hot, therefore I don't believe they are burnt.
Maybee something about the power supply went wrong?
Can you gibe me some instruction what to do? Can I check the Voltage regulators?
Was running the 180MHz file for about 30 seconds, then the miner aborted with IO errors after some succesful hashes.
I did a complete reset but the board does not come back
I had two 40mm fans above each heatsink, the did not get hot, therefore I don't believe they are burnt.
Maybee something about the power supply went wrong?
Can you gibe me some instruction what to do? Can I check the Voltage regulators?
Code:
root@esprimo:~/x6500-miner-org# python listDevices.py
0 AH00WOVU *
* means this device is currently available
root@esprimo:~/x6500-miner-org# ./program.py -v ztexmerge_166mhz.bit
2012-01-19 09:39:03 | Opening bitstream file: ztexmerge_166mhz.bit
2012-01-19 09:39:03 | Bitstream file opened:
2012-01-19 09:39:03 | Design Name: fpgaminer_top.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF
2012-01-19 09:39:03 | Part Name: 6slx150fgg484
2012-01-19 09:39:03 | Date: 2012/01/03
2012-01-19 09:39:03 | Time: 23:50:25
2012-01-19 09:39:03 | Bitstream Length: 3704054
2012-01-19 09:39:03 | Try open...
2012-01-19 09:39:03 | Device 0 opened (AH00WOVU)
2012-01-19 09:39:03 | Discovering JTAG chain 0 ...
Traceback (most recent call last):
File "./program.py", line 167, in
jtag[chain].detect()
File "/home/snpr/x6500-miner-org/jtag.py", line 81, in detect
raise NoDevicesDetected
jtag.NoDevicesDetected
root@esprimo:~/x6500-miner-org#
0 AH00WOVU *
* means this device is currently available
root@esprimo:~/x6500-miner-org# ./program.py -v ztexmerge_166mhz.bit
2012-01-19 09:39:03 | Opening bitstream file: ztexmerge_166mhz.bit
2012-01-19 09:39:03 | Bitstream file opened:
2012-01-19 09:39:03 | Design Name: fpgaminer_top.ncd;HW_TIMEOUT=FALSE;UserID=0xFFFFFFFF
2012-01-19 09:39:03 | Part Name: 6slx150fgg484
2012-01-19 09:39:03 | Date: 2012/01/03
2012-01-19 09:39:03 | Time: 23:50:25
2012-01-19 09:39:03 | Bitstream Length: 3704054
2012-01-19 09:39:03 | Try open...
2012-01-19 09:39:03 | Device 0 opened (AH00WOVU)
2012-01-19 09:39:03 | Discovering JTAG chain 0 ...
Traceback (most recent call last):
File "./program.py", line 167, in
jtag[chain].detect()
File "/home/snpr/x6500-miner-org/jtag.py", line 81, in detect
raise NoDevicesDetected
jtag.NoDevicesDetected
root@esprimo:~/x6500-miner-org#
Hi,
The other two available fpga bitcoin boards have an open design - I can reuse them for different purpose, re-program or sale them as fpga dev kits if I decide to stop mining with them.
I would at least like to generate my own bitstream with your board, will this be possible? Will you release the schematic?
The other two available fpga bitcoin boards have an open design - I can reuse them for different purpose, re-program or sale them as fpga dev kits if I decide to stop mining with them.
I would at least like to generate my own bitstream with your board, will this be possible? Will you release the schematic?
Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
Hi guys,
I have finished the first version of my C port of TheSevens pyminer
fpga-cminer 0.1 : http://pastebin.com/JRPsnpeJ
It is not as advanced yet but it works on systems without python.
My next step is a I2C interface for mutliple boards with small hashing power, as I have plenty of them
b.r
Lazarus
I have finished the first version of my C port of TheSevens pyminer
fpga-cminer 0.1 : http://pastebin.com/JRPsnpeJ
It is not as advanced yet but it works on systems without python.
My next step is a I2C interface for mutliple boards with small hashing power, as I have plenty of them
b.r
Lazarus
That one would rock!
http://cgi.ebay.de/Micro-Super-Computer-3-x-Altera-Stratix-III-FPGA-/130500717600
sadly its above my budget
http://cgi.ebay.de/Micro-Super-Computer-3-x-Altera-Stratix-III-FPGA-/130500717600
sadly its above my budget
Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
Hmmm
I have a delta of 15s with the test pattern - thus ~3MH/s on my Lattice ECP33
15s * 94.738 gives a quite large number, therefore the min(60) hits and I end up with 47s job intervall.
Whay is it right to take this short path to 60s? I guess this was not ment to run on delta > 1.
I have a delta of 15s with the test pattern - thus ~3MH/s on my Lattice ECP33
15s * 94.738 gives a quite large number, therefore the min(60) hits and I end up with 47s job intervall.
Whay is it right to take this short path to 60s? I guess this was not ment to run on delta > 1.
Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
TheSeven, could you explain what you're doing here?
I am porting this stuff to C and i am wondering about those magic numbers like 94.738 and 45.335163.
And why to multiply with 0.8 ??
I am porting this stuff to C and i am wondering about those magic numbers like 94.738 and 45.335163.
Code:
self.log("Endtime: %f\n" % endtime)
delta = (endtime - starttime) - 0.0145
self.mhps = 45.335163 / delta
delta = min(60, delta * 94.738)
self.log("%f MH/s\n" % self.mhps, curses.A_BOLD)
self.fpgajobinterval = min(self.fpgajobinterval, max(0.5, delta * 0.8 - 1))
self.fpgapollinterval = min(self.fpgapollinterval, self.fpgajobinterval / 5)
self.log("FPGA job interval: ")
delta = (endtime - starttime) - 0.0145
self.mhps = 45.335163 / delta
delta = min(60, delta * 94.738)
self.log("%f MH/s\n" % self.mhps, curses.A_BOLD)
self.fpgajobinterval = min(self.fpgajobinterval, max(0.5, delta * 0.8 - 1))
self.fpgapollinterval = min(self.fpgapollinterval, self.fpgajobinterval / 5)
self.log("FPGA job interval: ")
And why to multiply with 0.8 ??
Im porting the miner.py to C because I have no python on my embedded system.
Can someone explan me what this python snipped is all about:
b.r.
LazarusLong
Can someone explan me what this python snipped is all about:
Code:
self.fpga.write(struct.pack("B", 1) + job.state[::-1] + job.data[75:63:-1]
Does it mean bytes 75 to 63 are snipped out in reverse order???b.r.
LazarusLong
Re: Official Open Source FPGA Bitcoin Miner (Smaller Devices Now Supported!)
I now have a bitfile for the atlys board (spartan 6 - lx45) with depth:=2 and 50mhz
The only problem is, that miner.py refuses to communicate over the serial port.
It detects the core, but when it starts "Measuring FPGA performance..." it produces and timeout: "Timed out waiting for FPGA to accept work"
@TheSeven: any idea how to debug or solve the problem? is the miner.py code working for all depths and frequencies?
You'll need to adjust the pin locations for clk_in, rx and tx in the UCF file, and adjust the clock divider for the serial port for the 50MHz frequency.The only problem is, that miner.py refuses to communicate over the serial port.
It detects the core, but when it starts "Measuring FPGA performance..." it produces and timeout: "Timed out waiting for FPGA to accept work"
@TheSeven: any idea how to debug or solve the problem? is the miner.py code working for all depths and frequencies?
Replace "10000010001" with "0110110010" and "11000011001" with "01010001011" in uart.vhd.
And I should probably publish the new version of my miner, it now supports multiple pools, long polling, etc.
TheSeven, can you give some lines on how to calculate the deviders, any formula?