Ah, so you're saying that as soon as the signal for one hash leaves a transistor to go the next, the next hash is already incoming to that first transistor? Then the limit on clock speed is only the switching speed of one transistor, and so there's no way to really improve it? Would reducing the number of transistors just reduce the power consumption then?

Yeah, so currently a double hash is like 2000+ sequential operations, so there's a maximum frequency you can operate while you wait for the output. If you somehow could use just 1000 gates, you could run it ~twice as fast, right? Or is there some other limitation?

I haven't followed bitcoin since before ASICs, and I remember when people were trying to squeeze every optimization they could out of the hashing algorithm in the gpu codes.

I didn't know where to put this thread, but my question is about how ASICs are optimized. If I managed to find an extremely good optimization that somehow halved the instruction count needed for a double hash, is that interesting to the ASIC designers? I would think it would save power consumption at least. If not halving, what ratio is interesting? A tenth?