Impressed by the low power at only 65 Watt at 178 Mhsh or so.I am pretty sure that most of the miners here will be more than willing to see that miner go to 200-300 watt and see 4x or 5x the hash rate it currently has.That can be the miner all people living in countries like Germany and alike are waiting for because they pay really high electricity cost.I also hope you have success in your work and hopefully we will see more FPGA with better 16 GB HBM2 memory in not the so distant future.
The JC board will not take that much power. You can get a little more from water cooling but 200-300 watts will most likely end in tears or fire!
That's not true, the JCC2L boards can take 450W (not per FPGA, total, so 225W per FPGA).
will your bits be available for FK33 also , if/when its out ? good to see that there is some development for sqrl stuff, since seems like they are gone permanently in all shapes and forms.
An FK33 is too small for this implementation.
I think you need to go look at the backlog in semi conductor production before you say a few months to asic. More like a year+ at this point. Fpgas fork easily unlike asics. But again it is not the threat you claim it is….there simply isnt the magnitude of volume of fpgas and the cost is sufficient to keep it that way for now.
They will only tell they are producing it publicly if they plan to sell or market it as to sell on a set date, many produced asics in the past and kept for themselves for years till they decided to sell because they had something else better to let in their warehouse. Bitmain is known to do that, anyway, those practices are common known, not sure why you asked me to check semiconductor backlog, they ask for discretion here, when lots of money is involved and they dont want people to know then nobody will know about it. I said few months probably there are prototypes already.
This isn't always true. I mean, I'm announcing this one because I know of at least one other implementation, and people ought to know that it's possible.
Also, this implementation uses HBM2 memory, which would be *very* expensive to put on an ASIC. Not only do you need the HBM2 itself and an interposer, but you additionally need memory controller IP and such. It complicates a design massively.