Way2Go! I will keep watchin

Beans... missed it 09-09-2014 was a good day
These are very good hubs.

As a test, someone with ..say 4 or 6 TH SPLIT IT IN HALVES.

When stable running separate workers, shut em down.

Run one half set on a pool of your choice, the other worker here.

Run for two weeks, count the bitcoins and lets see what is up.

Removing all the variables, just the two pools in competition.

I really doubt there will be much diff...

=======

I just allow a little more power as in amps  6a 5v will do most all usb 2.0 10 port hubs, usb 3.0 12v hubs may or may not work all the time depending on brand, usb asics use usb 2.0 and 1.0 signaling protocol.

End the issue, get a eyeboot 49 port hub from klintay.

That Never Happens here, we are responsible for all our prodigy.. till all of a sudden

I would like to add, I had to do the serial numbering for XP usage.
W7 "virtualizes" ports just fine even if all devices have the same serial device numbers.

I also needed to remove all hubs and miners from machine to run the utility without errors, on XP.
Insert One USB Miner on XPmachine at a time and run utility.

ANT U1 & U2 also.

This seems to be a XP only issue.

Where is the PCB rear inch thick heatsink ? 70% of the heat goes thru the vias ??
Plus looks like your board is warping from pressure of waterblock...

Also On Carpet ? carpet holds heat in (insulator) place miner on stone or metal rack.

Congratulations ! Lots of new work

Will test here. W XP laptop and three hubs.

I will stay busy reading all those new links just posted, lots of good stuff therein,,,,
Did find the reason all are struggling, noone wanted to share info, till lately.
with a 6month lifespan on high end equiptment, they have no time to act like that.
Community shared it would have gone much faster.

Quote zefir:
Step-by-Step Bring-up Process
1) Physical
Most is depicted in the above figure, this is the prose version:

    chip is 1.8V only => use level shifter for all signals from/to host SPI interface
    VDD needs to be ~820-850mV with a max. ripple of 70mV (pilot run chips do not support undervolting)
    AVDD needs to be 1.8V with a max. ripple of 200mV
    power-up PLL settings are based on 12MHz reference clock; if you use a higher value do not start hashing without reducing system clock via PLL or you risk bricking the chip by overclocking it.
    if you have a multi-chip board, use a clock distribution device to drive them with a single oscillator
    heat-sinks on both sides of the chip needed, monitor and ensure surface temperature does not exceed 50°C
    HW reset is mandatory; RSTN needs to be pulled low for at least one second; ensure it was released for at least one second before the first command is issued

Having all alt coin mining machines "offline" and in storage, including wallets "gone cold".

Will have to wait and see where all this takes us. CORG is a keeper to me, so I will simply hold till something happens.

Right now 800mh plus script miners are coming out, should really see some big changes soon - both to coin algo's and miners.

To many coins not enuf time in life to care anymore, need scripted pool switching software for personal mining use. Not Multi Pools - Automated Multi Miners.

Thanks, I am not spi usb programmer, Just want to help out, and keep you barking up the right tree
Seems most industry devs already know most of this, It just hit the hobby level and I found it relevant to some of you guys diagnostic posts. AMT must also know this.

Seems all three have similar issues HF BA AMT. Would that boil down to Bitmine original design ?

1 SPI for each master slave.... Is correct way.

Here is some info on signalling issues you guys working on these are up against.

https://bitcointalk.org/index.php?topic=294197.msg6873065#msg6873065   

Quote from: blackarrow on May 21, 2014, 08:01:38 PM
"The issue is the SPI communication fails on the current backplane as soon as you attach more than 1 hashboard."

When problem solving, sometimes it helps to start with the basics:
http://www.embedded.com/electronics-blogs/beginner-s-corner/4023908/Introduction-to-Serial-Peripheral-Interface

Quote from: tempestb on Today at 02:08:55 PM
I wonder if by adding the second connection to the SPI if it is losing power?  It should be in third state I imagine.  Difficult to make any guesses without having any idea of what is going on. 

To put a finer point on it, from the article above (beginner's guide to SPI lol):

Quote
SPI's full duplex communication capability and data rates (ranging up to several megabits per second) make it, in most cases, extremely simple and efficient for single master, single slave applications. On the other hand, it can be troublesome to implement for more than one slave, due to its lack of built-in addressing; and the complexity only grows as the number of slaves increases.

Quote from: fivejonnyfive on Today at 02:54:28 AM

I'll say it again:
Replace The Backplane with Wires
As in 1 (one) SPI channel PER HASHBOARD going direct to a controller. I hope to god you didn't have all the hashboards sharing a common bus on the backplane before - because I can't imagine trying to get that to work.

Quote from: blackarrow on Today at 07:07:46 AM
Quote from: fivejonnyfive on Today at 02:54:28 AM

I'll say it again:
Replace The Backplane with Wires
As in 1 (one) SPI channel PER HASHBOARD going direct to a controller. I hope to god you didn't have all the hashboards sharing a common bus on the backplane before - because I can't imagine trying to get that to work.

Dear Jonny,

The PCIE connector has 98 pins and there are 5 connectors in each case.

If you still believe that this can be done even on one X3 (not to talk about mass production) you are welcome to come to our office and try to do this yourself.

Regards!

Quote from: Vcore:
Surely most of those 96 pins are power and the backplane doesn't have any problem with power does it?
So why not cutting the spi traces and running wires only for the spi?
It might not be elegant but depending on the pcb it might be workable (ie, desoldering something and putting an spi only connector glued to the board) or at least it works to test it.

....

Which brings us to our first unknown string variable "variance"

As in pool size or power.

There are more...

I would like a opinion on this mergecoin theory:
Placed by another member in another thread...

""I will let you in on a little secret: The actual purpose of merge-mining is to increase the hashrate and so reduce the amount of coins any one party receives from mining. This induces scarcity which in turn is expected to encourage the price to increase.

If you merge-mine a coin with equal hashrate, you are then doubling your coins hashrate (assuming you get that whole community to merge-mine your coin as well). This increases the difficulty, less coins to more people, price is expected to go up due to scarcity.""

Congrats on the 1 PETAHASH, I know it was a goal, Well Done Doc, nice pool.
Go Koi !

Hello!

Still Need water cooling and rear heatsink info (recommended &/or supplied).
Wire connectors supplied ? for using server supplies (2000w are cheap)
4 PCIE 16 or 14ga 24" long pigtails would do.
Chip price was posted @ 800 per unit, any way to get Intel or AMD TI ect on this raping going on

As stated power use is irrelevant, if it cannot pay for power for many years I would be worried.
I still profit on ant U1 BE and U2.. Can buy one U2 a month at current diff.
@750gh for this unit I could buy 30-50 U2 a month based of the 15gh I am at now.
hehe low budget miner needed...

 

Thanks, the link led to coin info, and a deja vu. I got interested in this coin as when I was younger (1970's)
I had a friend who liked Newfoundland (newf's Huge dogs) then got into Corgi's later on.
His name was John Tomlinson.  hehehe Not Jon but way to close funny world...

Solid copper spacers to raise ASIC level above other components.
However the small SMT components may then overheat due to lack of airflow.
Immersion is the only cureall for this design of boards top level.

Holddowns for the small sinks as suggested world take a board revision to accomplish.
I think since that chip is isolated (other chips show no signs of overheating), was a short from dislocated backplane or other damage occurred during ship.

HiJacking ? Do you mean the redirect bug ? If so it is being dealt with as we speak. Dev's are on it.