Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217
--> MC_SEQ_MISC1
-- MR0
WL = 3, CL = 22, TM = 0, WR = 23, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0
Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617
--> MC_SEQ_MISC1
-- MR0
WL = 4, CL = 23, TM = 0, WR = 25, BA0 = 0, BA1 = 0, BA2 = 0, BA3 = 0
-- MR1
DS = 0, DT = 1, ADR = 1, CAL = 0, PLL = 0, RDBI = 0, WDBI = 0, ABI = 0,
RES = 0, BA0 = 0, BA1 = 1, BA2 = 0, BA3 = 0
I think you are off by +1 with the MR0 CAS latency. SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.
Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?
The CAS latency in MR0 is just four bits (A3-A6), so it is based on a table lookup. H5GQ1H24AFR supported all possible latencies from 5 to 20. Micron's EDW4032BABG brief says "Programmable CAS latency: 627", so some latencies in the range cannot be programmed. I don't have a Samsung datasheet for the K4G4 series (or any Samsung for that matter), so I would have to reverse-engineer the values from the straps by comparing the MR0 values to CL from SEQ_CAS_TIMING.
Timings samsung k4g80325FB
2000 777000000000000022CC1C0031F67E57F05711183FCFB60D006C070124081420FA8900A00300000
01E123A46DB354019
tcl: 24=>25 - MISC1: 0x20140824 0010 0000 0001 0100 0000 1000 0010 0100
1750 777000000000000022CC1C00106A6D4DD0571016B90D060C006AE70014051420FA8900A00300000
01B11333DC0303A17
tcl: 22=>23 - MISC1: 0x20140514 0010 0000 0001 0100 0000 0101 0001 0100
1625 555000000000000022CC1C00CE616C47D0570F15B48C250B006AE7000B031420FA8900A00300000
0190F2F39B22D3517
tcl: 21=>22 - MISC1: 0x2014030B 0010 0000 0001 0100 0000 0011 0000 1011
1500 555000000000000022CC1C00AD595B41C0570E14B00B450A0068C70003011420FA8900A00300000
0170E2B34A42A3116
tcl: 20=>21 - MISC1: 0x20140103 0010 0000 0001 0100 0000 0001 0000 0011
1375 333000000000000022CC1C008C515A3DC0570D132DCB74090048C7007A0014207A8900A00200000
0150D293197282E15
tcl: 19=>20 - MISC1: 0x2014007A 0010 0000 0001 0100 0000 0000 0111 1010
1250 333000000000000022CC1C004A494937B0570C12294A94080046A700720E14207A8900A00000000
0130B252D89252A14
tcl: 18=>19 - MISC1: 0x20140E72 0010 0000 0001 0100 0000 1110 0111 0010
1125 333000000000000022CC1C0029414831A0570C1125C9B3070046A6006A0C14206A8900A00000000
0110A21287B222614
tcl: 17=>18 - MISC1: 0x20140C6A 0010 0000 0001 0100 0000 1100 0110 1010
1000 333000000000000022CC1C000839372B90570B102148D30600448600620A14206A8900A00000000
00F091D236D1F2213
tcl: 16=>17 - MISC1: 0x20140A62 0010 0000 0001 0100 0000 1010 0110 0010
900 333000000000000022CC1C00E7B4362780570B0F9F072306002485005A091420DA8800A00000000
00E081A20621D2012
tcl: 15=>16 - MISC1: 0x2014095A 0010 0000 0001 0100 0000 1001 0101 1010
600 333000000000000022CC1C00A520241A40570B0B97051204002264003A051420CA8800A00000000
00906121541151810
tcl: 11=>12 - MISC1: 0x2014053A 0010 0000 0001 0100 0000 0101 0011 1010
400 333000000000000022CC1C006394121120570A091144B102002042002A021420AA8800A00000000
006040C0E2B10120F
tcl: 9=>10 - MISC1: 0x2014022A 0010 0000 0001 0100 0000 0010 0010 1010
250 333000000000000022CC1C00628C110B10570A080EC3B00100204100220114209A8800A00000000
0040308091B0D0F0E
tcl: 8=>9 - MISC1: 0x20140122 0010 0000 0001 0100 0000 0001 0010 0010
Hope it helps, boring part of the work done

BTW, i think this bios has a 2250 strap also, once i get to 2250mhz mem it gets back to 26 mh even after copying 1750 straps to 2000
Comparing it seems bits 25-28 of misc1 are tcl-5 up until 1375 where it gets back to zero, then the only bit that changes in misc8 is bit 29 that turns to one in 1500 and stays on afterwards up to 2000, so that may be the msb