Quote from: ChipGeek on December 11, 2012, 04:24:53 PM

Quote from: ab8989 on December 11, 2012, 10:14:18 AM

https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html

But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.

The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.

You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.

What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.

I also wonder which phase of production the fab is in. Mask set done? Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.)

If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.

I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments.

fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days.

I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed.