Quote from: ihtfp on April 18, 2013, 04:56:34 PM

Quote from: AJRGale on April 18, 2013, 02:39:54 AM

So, looking into this whole mining with fpga system, and this code you people are working on, what is the required Logic cells/gates required for a full roll out? also whats the smallest unit you can get it running on? (the bare minimal for a half roll out (what ever you call it?))

I just want to dip my toe into the FPGA mining with a cheap and nasty chip set Wink

just tell me to piddle off else where if its the wrong spot to ask

AJRGale,
I think you'll want at least a Spartan6 LX150. This is the cheapest device I would use. I would only run a fully pipelined implementation -- one that can do one hash per clock cycle. If you can get a hold of a Kintex7 or Virtex7 board you'll be a lot better because you can instantiate more miners.
fpgaminer has posted a lot of useful code on github.
I don't speak Altera, so not sure on specific devices.

so 150K gates? like a Cyclone V? (no idea what gates to logic cells ratios really are) ...so that means 75K gates for half miner?

Ether way, cant find a Spartan6 LX150, can find a http://www.adafruit.com/products/451 "DE0-Nano - Altera Cyclone IV FPGA starter board "
a miner could run on it, buut, only the smallest one to what I've read out of here, at 5Mh/s...

maybe i should look at the code and work out how to use the dev suite, maybe it might tell me what it needs to run i have no idea what I'll be looking at though :/