Quote from: qed on June 12, 2011, 01:46:43 AM

Quote from: ahtremblay on June 12, 2011, 12:59:00 AM

Quote from: qed on June 12, 2011, 12:33:21 AM

Quote from: ahtremblay on June 11, 2011, 07:31:17 AM

I have a rudimentary design right now. It is the circuit in gate array format that I designed. It is not a final design by any means, but it allows me to identify the key bottlenecks of the system, calculate gate propagation, maximum clock speed, etc. So what I have from this is; 8MHz clock, 1 hash per clock, and 100 pipelines. This could fit on low volume production run for 27$ / ASIC from TSMC. You then need to add the cost of shipping, putting it on a PCB board and add a controller, + design cost for the lithography. So basically, 800 Megahash/s, for 57$ or so (+ design costs spread across the production line). And that is without the optimization to the main bottleneck (a 7 input adder) that I am working on. So it is encouraging.

You can easily add 4-5 ASIC on each PCB board improve the Hash/$ ratio. So, with 5 ASIC per board, you would get 4GIGAHASH/s for 165$ (+ design cost). (the price of a 5850). Essentialy it makes gpu mining obselite.

Absolutely impossible.

Hello, care to elaborate a little more?

I have developed in Xilinx ISE and from my experience that's way off. How many gates do you have? To have 1 hash/clock it must be insanely big, and you have to multiply it by 1000 (as you said). Hoe did you guess the production cost?

Even without knowing anything about algorithms Bitcoins and other stuff, the fact is: Commercial solutions are slower and more expensive, how a person with no experience make something better, faster and cheaper?

The performance numbers sound reasonable. I have no idea why he only gets 8MHz, but this sounds like it can be improved. For a full pipeline you need roughly 100K flipflops plus all the logic. 100 times that would be 10M flipflops plus logic, which would be a rather big ASIC, but it's certainly possibly.

I had a co-worker try an Altera HardCopy synthesis and that one ended up with 20 pipelines running at >200MHz each, yielding >4GH/s per chip.

I don't trust these cost estimates at all though. The ASIC price estimate might be sensible for >10000 volumes, but the board, host interface and assembly cost estimated at $30 seems to be impossible. The VRM alone will cost that much.