Now that there is new data on die size, I updated the GH/wafer table:
Die size is less than 336mm2.Code:
wafer(mm) chip process(nm) die(mm^2) GH/s(per die) DpW GH/s(per wafer)
300 KnC 28 441,00 25 128 3200,00
300 bitfury 55 14,44 2 4717 9434,00
300 bfl 65 56,25 4 1167 4668,00
300 asciminer(?) 130 17,50 0,333 3877 1291,04
300 avalon 110 16,13 0,282 4214 1188,35
300 asciminer(?) 130 21,7 0,333 3112 1036,30
(DpW, die per wafer; yield percentage not taken into account)
300 KnC 28 441,00 25 128 3200,00
300 bitfury 55 14,44 2 4717 9434,00
300 bfl 65 56,25 4 1167 4668,00
300 asciminer(?) 130 17,50 0,333 3877 1291,04
300 avalon 110 16,13 0,282 4214 1188,35
300 asciminer(?) 130 21,7 0,333 3112 1036,30
(DpW, die per wafer; yield percentage not taken into account)
I think 18x18mm
Another detail for a better table. As far as I know, 130nm(110nm) are still manufactured based on 200mm wafers. 65nm(55nm) nodes were the first built with 300mm.
Ummmm. KnC is doing a 28nm process and getting only a third of the GH/s per wafer that bitfury is getting at 55nm?
HERE
The slides says that it's only one die, containing 4 self-contained cores (quads).
A more correct table looks like that:
-> KnC die size estimated based on technology scaling
-> Source for Bitfury die size? Seems to be wrong. And chips are specified for 5GH/s per chip (not 2 GH/s)
Code:
wafer(mm) chip process(nm) die(mm^2) GH/s(per die) DpW GH/s(per wafer)
300 KnC 28 120,00 100 589 58904,00
300 bitfury 55 14,44 2 4847 9694,00
300 bfl 65 56,25 4 1244 4976,00
200 asciminer(?) 130 17,50 0,333 1795 597,74
200 avalon 110 16,13 0,282 1947 549,05
200 asciminer(?) 130 21,7 0,333 1447 477,51
(DpW, die per wafer; yield percentage not taken into account)
300 KnC 28 120,00 100 589 58904,00
300 bitfury 55 14,44 2 4847 9694,00
300 bfl 65 56,25 4 1244 4976,00
200 asciminer(?) 130 17,50 0,333 1795 597,74
200 avalon 110 16,13 0,282 1947 549,05
200 asciminer(?) 130 21,7 0,333 1447 477,51
(DpW, die per wafer; yield percentage not taken into account)
That is the real 28nm world!
It is more likely that each chip is 4 DIE.
If die has 4cores with total size is 120mm^2 . 20 wafers are more than 1PHs. Why go to work on the second gen?
No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.
Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!
It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?