Quote from: Ytterbium on July 31, 2013, 08:55:33 PM

Quote from: Simon Barber on July 31, 2013, 08:48:18 PM

We believe one previously announced effort at 28nm is using eASIC, so their cores are *much* bigger than they have to be. Of course their startup costs are much lower too, but it impacts the performance a lot. Look at the η-factor for other 28nm designs.
https://bitcointalk.org/index.php?topic=119668.0

The η-factor thing is total nonsense for ASICs if they're thermally limited.

Also, KnC is using a standard cell design, not an eASIC 'easycopy' or whatever. eASIC is just one of the companies they work with.

Just for correctness. Taken from:

http://www.easic.com/Spatr7ve/website-wp1/wp-content/uploads/2011/05/easicopy-ASIC-Product-Brief.pdf

"The easicopy design flow is shown below. At the front end it requires a eASIC Nextreme or Nextreme-2 synthesized netlist and
an SDC timing constraints file. After initial synthesis, the design is taken through a traditional cell-based ASIC flow by eASIC
engineers. This includes Design For Test (DFT) insertion and synthesis, and then back-end physical implementation which includes
floorplanning, I/O ring design, power mesh design, timing driven place and route, timing closure, parasitic extraction, final STA, and
tapeout readiness."

That means, the eASIC easycopy service is a normal standard cell ASIC design flow. eASIC offers structured ASICs (FPGA hardcopies) and standard cell ASICs.

So theoretically eASIC would be a partner for a standard cell ASIC too. But I would not choose them for a 28nm implementation, because they have no proven first time right tape-outs in this technology node and there is a hard learning curve for that kind of implementations.