Quote from: Vbs on August 07, 2013, 08:26:15 PM

Quote from: VinceSamios on August 07, 2013, 06:59:05 PM

Can somebody explain to me the suggestion that a "28nm ASIC" is basically just a 28nm FPGA... I read the eASIC press release to mean they've simplified the process of designing ASIC's to a level on par (in simplicity terms) to coding an FPGA? In other words "We've got software which basically designs the ASIC for us, based on an algorithm" rather than "our 28nm asic's are actually fpga's"

Maybe I'm missing the point here, but a 28nm ASIC is an ASIC... There's absolutely no way anyone could get 16GH on an FPGA chip, or even a semi-FPGA chip (whatever that is). If we compare the "real 65nm ASIC" produced by BFL, at 4.5GH, with the apparently "not real 28nm ASIC" running at 16GH, by your suggestion the concept that a 28nm chip can hash at 16GH is impossible.

I'll freely admit I'm not an engineer, but I am a logical person, I code, and I understand the concepts and differences between FPGA's and ASIC's. What's being suggested simply doesn't compute.

Hehe, very simple.

In an eASIC nextreme you remove the SRAM Programmed Routing of an FPGA and replace it by a real metal layer, so you not only get rid of the logic gate controlled routing bottleneck, you also gain more space on the chip for the logic gates that do the actual work.

Do you have any insight into how this differs from the "better" cell-based ASIC that I keep seeing referenced?