Quote from: Ytterbium on August 18, 2013, 01:16:41 AM

Quote from: mrb on August 18, 2013, 12:52:13 AM

Quote from: willphase on August 18, 2013, 12:09:45 AM

Quote from: BFL-Engineer on August 17, 2013, 11:56:18 PM

Due to double node jump, the max power should be 0.77W/GH (3.1W/GH divided by 4). Based on everything we know from any chip industry (FPGA, CPU, GPU, etc), that should be the ceiling in power-consumption.

Hi Nasser,

Brave of you to dive into the BCT feeding frenzy!

I'm curious about your numbers - 0.77 * 600 = 462W - how come it says 350W on the website?

What he is saying is that just the theoretical power efficiency increase alone gained from 55nm to 28nm should guarantee 0.77 W/GH. But he also said they improved the design (maybe fewer transistors, a "sea-of-hasher" design like bitfury, etc), therefore it should be even lower than 0.77 W/GH.

There's no way that's true. Check out this paper: Power Consumption in CMOS VLSI chips

I stop you right there. Bitfury has a chip consuming 0.8 W/Gh/s and it is 55nm. So it is beyond any doubt that a 28nm chip (theoretically 4x more efficient) can increase efficiency to at least 0.77 W/Gh/s (which necessitates only a 1.04x improvement).