Quote from: bondus on October 22, 2013, 09:47:03 AM

Quote from: fpgaminer on October 20, 2013, 12:02:23 PM

Well I bit the bullet and tweaked the 0x86 register on one die. I tried a few different values, 0x0168, 0x0068, and 0x01ff. initc did not seem to throw any errors, and everything hashed like normal. I did not notice a difference in power consumption on any of the settings, so I can only assume the hash clock was not affected.

So ... there goes that theory.

Awesome job figuring out that checksum algorithm.

Take a look in /etc/init.d/cgminer.sh and you will have your answer to why nothing changed.
It is writing to the same SPI PLL registers by hand in there just before starting cgminer, not looking in the eeprom.

   for p in $good_ports ; do
   # Re-enable PLL
   i2cset -y 2 0x71 1 $((p+1))
   for c in 0 1 2 3 ; do
   cmd=$(printf "0x84,0x%02X,0,0" $c)
   spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
   cmd=$(printf "0x86,0x%02X,0x01,0xD1" $c)
   spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
   cmd=$(printf "0x85,0x%02X,0,0" $c)
   spi-test -s 50000 -OHC -D /dev/spidev1.0 $cmd >/dev/null
   done

The table for disabled cores is also stored in the eeprom at offset 0x4c and 192 bits forward.

Thx for the huge hint!

I can confirm it works.
150 Gh/s per module on Oct 4 VRM modules.
I have 2 Saturn doing a reliable 600 at the pool and 720 at the wall.

Along the way I managed to put to sleep and awaken individual die.
I think this is the way to address the dead die issue.
I offered to discuss my findings with a KnCMiner engineer, no reply.
My guess/observation is it is a low priority for KnC to fix the dead die issue.
Sad if true.
The fix seems simple, monitordcdc knows, try different clocks when dead die detected.
I have tested many low current working solutions at stock speeds.

One problem I ran into is that every ASIC is different and the .sh threats them all the same.
One Saturn was easy and one I had to do a lot of hunting (not recommended)

My next step will be unrolling the afore mentioned program loop and try each module seperately and possibly each die seperately for maximum yield.

Trying any of this will VOID YOUR WARRANTY.
You might kill your miner AND have no warranty!
You have been warned.

I have an educated guess on the field width of the variables.

I treat them as 4 bit fields with some success.
If the middle one is 5 or 6 bits wide more finesse is possible.

The lowest 2-4 bits seem to control the output and/or loop divider.
Larger numbers more division (behaves like divider)
Has a major impact, compensate with what I am calling input/reference divider.

Middle nibble seems like 4 bits of loop control.
There may be more lower bits to this field, unconfirmed.
Larger is faster.
This is the one to fiddle with once the others are close.

Highest nibble 3-4 bits of what I call input/reference divider.
Larger numbers less division (behaves like add or multiply)

Start with the middle one only and watch the current!!!
Be ready to bail if needed.
Just stop modified sh and start unmodified one.
(you did modify the COPY of the file right?)

I might have the fields backwards but I get predictable results.

This is a dangerous game to play with an expensive ASIC.
You will VOID YOUR WARRANTY and might kill your machine.

Please refrain from simplifying the process for the masses, yet.
The edits are easy, the possibility of meltdown is real.
Further testing is needed.

Don't even think about editing this stuff on a Nov unit with 8 VRM's
There is easily enough power available to cook your ASIC.
It is also not the same file to edit.
Think twice about it if you have an Oct. with 8 VRM.
There is easily enough power available to cook your ASIC.

I use 47 A and 37 W as the max per die for 150 Gh/s per module.
Under 45 A and 35 W max with stock 144 per module speed.

The main use I have for the tuning suite is feedback.
The SPI clock @ 200k is plenty. Higher is fun but not very effective.
I looked with a scope, there is room to spare @ 200k.
I leave everything default until i get the ASIC clock happy.
Once the clock is happy the rest makes little difference and I only tune V for lower power.
VCO current is IMneverHO more important than all else.
It is significant, an Idle die uses ~15 A, much of that is the clock.
If you see a die with 0 A suspect a stalled clock.
There are even ways to occasionally unstall a stalled clock.
Make a small edit to the SPI clock and hit the apply button.

For the 'hardware' tweakers, I speculate 2 loop caps per die on bottom of board.
Next diff increase or so and I may take the iron and find out.

I spent a lot to find and document the details and pass them on, downtime is money.
You can help fund this research if interested.
Just point your miner to one of my workers for a few minutes.

For BTCGuild worker = tolip_ZsearchFund (PPS, best for short donations)
For GHash.io worker = tolip.anything (replace anything with your name if you like)

You can also use my reseller ID if you purchase a Neptune.

https://www.kncminer.com/?resellerid=206

Enjoy