Quote from: GPUHoarder on May 05, 2018, 01:51:47 PM

PCIe, even 4.0 for which backplanes are not yet available, is 8 or 16Gbps per transceiver vs 28 Gbps in the QSFP28s

I wasnt referring to 1525s though, I was speaking about other boards with 56+ transceivers exposed.

OK, so both Xilinx and Bittware boards have 16 xcvrs hooked to PCIe edge connector.

I mentioned "PCIe passive backplane" to emphasize that to use that we wouldn't need to obey the full protocol stack, including BIOS discovery & negotiation, transport layer packetization, etc. If the passive backplane contains only cards running "our" project then we could violate many if not most constraints in the official protocol.

All that really matters are the mechanical fit and signal margins on the electrical connectors. Given the simplicity and low cost it wouldn't be a problem to even cut some traces on the backplane PCB to make it electrically independent and improve noise margins by cutting out unnecessary copper.

Admittedly, I haven't played this game with PCIe devices, but in the past with older technologies all the way to PCI and PCI-X. Additionally, mining is essentially a lottery, so it can profitably tolerate bit error rates that wouldn't be acceptable in conventional applications. I get a sense that most of the devices utilizing QSFP28 are designed for either longer distances or higher reliability than what would be required here.

Or maybe you just thought about PCIe 4.0 motherboards instead of passive backplanes?