Quote from: HardwareCollector on May 10, 2018, 11:21:05 PM

Quote from: 2112 on May 10, 2018, 11:09:08 PM

Quote from: GPUHoarder on May 10, 2018, 10:52:31 PM

Quote from: HardwareCollector on May 10, 2018, 10:28:52 PM

As it relates to Ravencoin mining with FPGAs, OP will need to store over 300 million bitstreams to account for every possible combination. Better get back to the drawing board because this design will never work.

Partial reconfiguration - you dont need every combination, just every building block.

Yeah, for X16r coins thats 16^2=256, for X16s coins thats 16!/14!=240. Certainly doable.

Hmmm, two accelerator cards will be daisy chained with pipelining and their performance will magically double. I will believe it when I see it like all other claims made by the OP.

This isnt hard. I do it all the time for a few algorithms. Heres a contrived example - fill the scratchpad for CN7 on one FPGA dedicated to that, spitting out 2MB scratch pads all day long, and taking them back in and compressing / finalizing them. Total bandwidth for (example) 22kH is 343 Gbps. Thats achievable on lots of current hardware.

This makes it a lot easier build two sets of pipelines on two FPGAs for two related but very different set of operations. Doing all the things on two separate FPGAs couldnt achieve the same performance.

This was a back of the envelope example, but the Xxx algorithms that just chain more on to the process definitely lean them selves to this kind of operation. This (and memory bandiwdth, and easier cooling) is why my accelerator cards have 4x75W
Ultrascale + FPGAs and not one big Virtex. Interconnect on those is 256 Gbps.

Edit: Let me try to phrase this in a few words. Dont waste the extremely high bandwidth interconnect and resources inside the FPGA for something you can use the slow external interfaces to accomplish.