[...] For the FPGA, I suggest the
ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm
2) and should be sufficiently stable.
[...] The oscillator you've suggested runs @ 3.3V, we'd need a 2.5V unit.
The design as it is on dropbox and github calls for the clock to be connected to IO_L30N_GCLK0_USERCCLK_2, pin AB13. The clock is shared between the two FPGAs (no need to have a dedicated clock for each). I will put the oscillator into the design, so it is no longer routed to the MCU.
I'm not sure how you plan to do this, to do it properly you'd need to buffer the oscillator and/or series termination at each end to reduce reflections.
FPGAminer: certainly good news, when this board get's made, I'm sure one of them will go to you.