http://thumb1.photo.ndrive.naver.com/12466325518?type=m3&setidc=2&filelink=yfTmbvStTJqzcRbH2MfRorLctZzh5CYXzrBXVQnCTp7GYMsDdY39QL7tPvicDbfACA==&authtoken=vmXj1+V/HENT4jAODAk29gI=


Anyone need reference board PCB?

I'm selling reference board PCB with stencil.

Here is my site.

http://theminingware.com/

One, two, whatever.  I can't afford 500, so I want smaller quantities.  I'll buy as many as I can afford, once someone confirms that I can get them in prototype quantities. 

If you must know, I'm planning to build a single chip unit so I can figure out if I can even make it work.  If I can't get one chip to work, what business do I have testing a chain?  Once one chip works, I'll chain them together, look at efficiency and packaging, and go from there. 

Why the hate for cautious baby steps?

So what would you do with just one chip ?

A1 coin craft chips will be priced at $87.50 per chip + 8% fee

yes, minimum lots are 500 pcs.

No, the current version runs exactly the CoinCraft Desk which is driven by a RasPi over its SPI interface. To make it working over MCP2210, one would need to wrap the SPI interface (which is abstracted over spi-context.c already) over MCP2210. Should be easy to implement, alas I currently am too busy so look at.

Code merged into master cgminer, thanks.

That or they should do a kickstarter type deal where they flat out tell you, "Give us money, you're buying into our dream, you're funding our startup, when/if we make money you'll get a bigger kickback than regular Joe retail, also we'll give you a BA shirt that you can either wear with pride or wear with a sense of irony depending on how things shake out. We may soar, or we may crash and burn, but now you know."

...

Announcement: Clarification on my personal Involvement with Bitmine


Dear DIY folks and miners,

as written in the OP, with the chips I ordered and distributed here, I have been Bitmine's largest customer from the beginning. With my ongoing work as consultant for SW and support during bring-up phase, I must have made at least something right: I have been offered a substantial stake of the company's shares and with that since this week I am also a board member.


How does this change the DIY chip distribution?
Definitively only for the better. Running this proxy service for the community already turned out to be error prone and impractical for higher demands. With manual processing, I already messed several orders up (delaying them or sending twice). The first action implemented for that was to make sample chips available from Bitmine's online shop.

Now that the first wave of DIY volumes was delivered, I expect not much further demands for 50+ volumes - those with working design will sure go for 500+ chip orders. To keep the door always open for late comers, I will pursue the integration of smaller order quantities in the online shop.

From this position I have a better influence on Bitmine's day business, so if there is something that can be improved for the DIY scene (I know there is), please let me know, either by posting here publicly or via PM.



Thank you all for the trust and support so far,
zefir

The LTC3811 isn't an integrated switch regulator like the TPS53355 you see used in some other designs. It's a controller and gate driver like the ADP1850, so the maximum current the VRM can handle will be determined by the external FETs and inductors.

Update: 2-Chip Evaluation Board Reference Design published by Bitmine


I have been approached numerous times from designers asking for a A1 reference design. Today, Bitmine added their 2-chip eval board design to their GitHub repository.

We used this board for initial verification - it runs with the provided cgminer driver as is over RPi's SPI interface.

Progress update - 12 Feb 2014

also posted on:
http://www.blackarrowsoftware.com/store/progress-update-12-feb-2014.html
http://ecointalk.net/topic/511-progress-update-12-feb-2014/


Following customer feedback we will be posting regularly updates.


12 February 2014

1. Chip pinout complete. Received for review. We have confirmed to be ok.

2. Based on Verisilicon’s feedback we are upgrading the heatsink to the new specs

3. Improved X3 case to optimize functionality

4. Reduced the number of PCBs in X1 from 6 to 3 to improve reliability.

5. X1 hashboard has been reworked to support higher power consumption. We are now at version 3. Layout completed, starting rerouting tomorrow.

6. X3 hashboard has been redesigned due to case improvements. Completed schematics of the 3rd version of the board. Starting layout after routing of X1 board

7. Control board has been redesigned to use PCI connector instead of flat cable for improved reliability. Layout complete, rerouting tomorrow.

8. Aquired bespoke 3D printer. Initiated prototyping of new parts for improved functionality in X3.

9. Meeting with VeriSilicon

10. Tapeout reconfirmed on 20 Feb 2014

11. Package confirmed

12. Delivered all final details regarding case, heatsinks and fans, running final thermal simulation, due to be received at the end of this week

...

There are two levels of experience I can share. The first one is from the logical link layer / SW side (my domain): when I got the FPGA simulator to work on the cgminer driver I attached it to RPi's SPI interface, sent it a job and got a result returned. I was like 'whoa if that is how the real chip works, that will be easy'. Then when I got to test the driver on a real A1, the same driver still worked and the chip crunched the whole nonce range in 160ms. I was like 'whoa, this is incredibly easy!'. If you take a look at the initial cgminer driver, you'll see what I mean.

Then there is the productizing level - which is not my domain and I can only report from my experience with HW hacking sessions over lots of sleepless nights. There it turns soon out that the 'easy' preconditions the chip requires (as depicted here) are not exactly trivial to ensure. You might end up opening your Champagne bottle after seeing your board hashing for hours flawlessly - just to notice it stopped over night. And after endless debug sessions to find out that one chip reset itself since your power supply had a larger than tolerated ripple at a very specific temperature. Or that one single bit in inter-chip SPI communication toggled due to parasitic effects from adjacent PCB layers - which as result kills a chip chain in case a command is interpreted wrongly by the chip.


So in essence: yes, the chip is really that easy. Ensure you keep the requirements met and it will hash right away. As for communication, there is not much you can mess up there: I have been trying the RPi's SPI port, bit-banging over GPIO, or proxying the access over STM32 SPI port - all work with master SPI clocks between 5 kHz and 10 MHz.

To make a working product out of it is a different story then. Getting it to hash for some hours is still easily doable - but building a board that runs for months untouched under various environmental conditions is not. That is why Bitmine has not yet started shipping products. And that might be the reason we see only marto74 reporting back successful operation of his design - he has a great experience with his Avalon / BitFury boards and started off from a design with verified signal integrity. Others starting from scratch might need to learn first.

In retrospect my advice would be: follow a KISS approach; start with a single or 2-chip design first and ensure your DCDC is capable to keep up the required power stability (for reference: marto74 and Bitmine provide 50A); in a second step, copy paste that design to form larger chains. While the A1 is meant to be chained up to 250 chips, 8-chip chains seem to be a sweet spot between overhead and communication latency.


Good Luck.