I think Artix-7 would be the best one/most cost efficient to mine BTC on, Virtex is a bit of overkill, and a lot more expensive.

Zynq would probably be amazing as well though (I think)

I just updated the repo with a DSP48E1 design, for Kintex 7.  400MH/s using 80% of the DSPs, and ~25% of random logic.  I don't have an Artix-7 to port to, but I think they also have DSP48E1's.  I plan to start revamping the code base to better support multi-core designs and standardize the communication modules.  Hope to get my Kintex up to at least 1GH/s by throwing in two regular hashing cores.

Ongoing panic sell

The Instawallet service is suspended indefinitely until we are able to develop an alternative architecture.

Our database was fraudulently accessed, due to the very nature of Instawallet it is impossible to reopen the service as-is.

High scam risk! This is a self-moderated topic. The original poster can delete replies, including ones which point out fraud or dishonesty by them. If you do not want to be moderated by the person who started this topic, create a new topic.

Excuse my non-technical, conceptual-only questions / thoughts / checking if I have this right in my head:


1)  There was no *permanent*  "double spend" right?   i.e. the transaction on the .8 fork would have eventually been orphaned / dumped / never credited to the address specified in the .8 block?

2)  The risk here (and reason why SwC shut off all deposits / withdraws for a few hrs until this was resolved) was that during this very odd period a sophisticated user could use multiple 0-conf services that would all at the same time believe they were getting the same coins, but after the blockchain becomes 1 again only 1 of the transactions would actually be included in the "real" blockchain?

It is also a huge issue that those suggesting we need the protocol spec are brushed off with the "you don't get it" nonsense by elitist devs.
Bits and pieces, some expired, are scattered around Wiki. Is that the best we can do?
@MP: would you be willing to lead the effort of formulating the current protocol spec?

It's actually about half of that. About half of those people shouldn't have found blocks and only did because the person who should have mined the block was working on the other chain.

Think about it this way, for each block in the fork, someone mined the block in the 0.7 chain and someone mined it in the 0.8 chain. About half the time, the right person got it (because the forks merged when the work in them was roughly equal), and they still have it. About half the time, the wrong person got it and the right person lost it in an orphaned block.

It's not ASIC resistant at all. You could make an ASIC for LTC if you seriously wanted to and though it was worthwhile. What you mean to say, more precisely, is that Bitcoin specific ASIC's (SHA-256) will not work for LTC.

Almost three hours later, and even later in the evening in EU, you posted

Avalon went with a very simple chip on a large(110nm) process. I imagine this strategy gave them very high yields out of the wafers because of the small chip size. This came at the cost of a large PCB to route to all the chips.

Once Apple discovers how it is being used it will be banned. It doesn't matter what gimmick is used to camouflage the intended functionality. Or if you found a flaw in the TOS that means they should allow your app, they will ban it anyway, and maybe update the TOS, if they feel like it.

And FYI, FPGA board vendors don't talk about power consumption at the wall, but at the 12V level, after the AC/DC PSU.

After months of work, finally I build a FPGA mining cluster using the board "Icarus".
each board has 2 XC6SLX150 -2FGG484I on it, generates a 380MH/s hashing power. 19.2W (full load working) / 3.4W (idle) power consuming (board input, without fan). here a detail spec table:

Technology: Spartan6 -LX150 -2I (or -3C)
speed (MH/s): 380
$: 569 (1) / 469$ (multiple of 30) (-5$ if you do not need the adapter, recommend for bulk orders, they are heavy)
W: 4.5 for idle / 21 for full load. (notice this is the on wall power, include the adapter losses and fan)

ASIC's are an unstoppable part of any cryptographic 'coin' as it gets more accepted and widespread. It would seem that at the moment Litecoin is 'safe' from ASIC's and can only be mined by GPU's, but an ASIC is sure to come if Litecoin gains fame and widespread acceptance like Bitcoin does.

I'm happy to announce my involvement with the 100TH Mine project, as hosting provider of choice!  This is a great project - BitFury has the design doing simulations already and the project is on track for mining in the June/July timeframe.  What I like about it is the price point - at $5/GHs, it amounts to 200GH/s for the same $1000.  I think its a worthy place to put your hardware dollars, especially if you got aced out of bASIC, BFL or Avalon.

For those of you who haven't checked out BitFury's FPGA project: http://www.bitfury.org/bitfury110.html

One thing to make very clear: this is not a reborn bASIC project, does not use Tom's chips, is not related in ANY way to bASIC.


https://bitcointalk.org/index.php?topic=140366.0

Not true at all. That bubble happened precisely because of regulation. Banks were practically forced to lower lending standards by Freddie and Fannie, not to mention the FED key interest rate affected mortgage rates to get artificially low enabling many to borrow who couldn't afford it. All Wall Street did was feed upon this circle and meet a demand that was created by the government and no one else. It's called moral hazard, look it up.

However that ignores the bigger picture, namely the amazing and astounding history of Freddie and Fannie from the 70s and the knock on effects.  My oversimplified understanding of it is of the way in which those government-set-up institutions got used to force lenders to lend irresponsibly to fulfill political agendas.

Well, I don't remember Pirate refunding 2/3rds of what was owed before running off with the rest, but I could be wrong.

I kinda agree with this sentiment. But why whine? Call BitSyncom, ask what MOSFETs and inductors he needs, raid the nearest RadioShack and Fry's and negotiate with him an exchange of components for finished product. If needed fly them himself to China in carry-in luggage.

I wanted to have a bit more information for this update, but it looks like I will have to wait until tomorrow to talk to a couple people.

The most important thing I wanted to convey to people at this time was that we have changed our initial "batch" from 12 wafers to 6 wafers, or to be more specific, it's apparently always been 6 with the additional six scheduled for about 1.5 weeks after that. Due to the short time frame between the two, there was a miscommunication as to the actual number of wafers being delivered in the first round. I don't know that this will affect any sort of shipping, since the next set of wafers will be done about when we are ready to start assembly on the first set.

The 6 wafers is actually a good set point for the "first batch" shipping, so the 1/3 plan will be implemented for the first 6 wafers and the remaining wafers will then all be FIFO. The first 6 wafers should cut into the pre-order orderbook by a decent chunk, but it obviously won't satisfy them all. We aren't sure what our yield will be on the wafers, we are running on an 80% yield speculation, but it's likely our yield will be much, much higher than that. With our design, we can have a core in a chip disabled due to dust or what have you and just bump up the other 15 cores to compensate and/or use it for a Jalapeno, so our yield will likely be much closer to 100% than other ASIC projects with more complicated chips.

We should see the bulk of what remains of the 75k chip run about 2 weeks after that, so about the time we are done shipping the other 6 wafers worth we'll have the bulk of our chips arrive and we'll start assembling/shipping those.

The bumping situation is mostly wrapped up at this point, so there should be no problem there. I know there was some talk about the final mask with regards to the bumping and that it may push the date of the chip completion back a couple days, but it shouldn't impact the timeline to speak of as a couple days on either side of the 31st of January shouldn't really make much of difference, being as it's basically a weekend and is in transit anyway. I am hoping to have confirmation with regards to that tomorrow (Monday).

I obviously haven't left for the fab yet, and Mondays call will determine when/if I leave. We have changed our bumping facility from the left coast to the right coast (North Carolina), so we may have the 6 wafers overnighted via courier to the bumping facility vs me picking them up and couriering them myself, although I will be meeting them at the bumping facility and making sure they don't sit around for a couple days while some guy eats and egg salad sandwich and wonders why there's a "priority!" box on his desk.