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Showing 16 of 16 results by xbaby
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Board Hardware
Re: Avalon ASIC users thread
by
xbaby
on 24/05/2013, 12:20:25 UTC
My avalon unit has  the exactly same issue as yours. I'd like to ask if the test firmware posted by xiangfu related to this issue?

I am using firmware 20130419. Unfortunately, I don't recall the previous firmware version I was using.

Prior to the upgrade on May 5, the Avalon unit ran without any problems.

However, after the upgrade, the miner has stopped hashing twice, and the only way to recover is with a cold reset. Is this a know issue?

Cheers!
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Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 18/05/2013, 16:48:52 UTC
the 300MHz result was just compiled with no timing error. in next few days, I'll program it on board to see if it could really run perfectly.

some update on the latest progress:

    I must say the 300MHz result was achieved with no clock pin constrained. after bind the clock pin to real pin location (and I use a 25MHz crystal), It's very hard to meet above timing parameter. the best result I've achieved is 275MHz by now. a little bit strange.

    And, to make my xc6vlx130t board actually work with a mining pool, I finished some hard work. the jtag_comm.v jtag / host communication code has some issue on Virtex6 BSCAN engine, and I've made a patch for it. currently, the board can work perfectly using the MPBM host software, with hash rate about 280MH/s, and about 11w wall power usage for 1 pcs lx130t FPGA chip.
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Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 10/05/2013, 05:52:28 UTC
the 300MHz result was just compiled with no timing error. in next few days, I'll program it on board to see if it could really run perfectly.
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Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 10/05/2013, 01:23:12 UTC
Oh, what speed grade did you use for the V6?  All my boards with 130s and 240s (ml605) are -1, so if you used -3 that could explain the big difference in the quality of the results.

my board have 2 pcs 130T devices. the speed grade is -2I. so your design with DSP48s really have some speed and power usage advantage. BTW, can your design be synthesized on XST?
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Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 09/05/2013, 13:21:50 UTC
Quote
Thanks for you hint. I've already tried SmartXplorer with default 7 built-in strategies, but can't achieve above 160MHz result. so, you mean I should use the cost table method to brute force it? thanks.
Yup.  For reference, the released bitstreams took days/weeks to compile.

xbaby,

You can also try to floorplan the DSP48s if you want to cut your runtime.  To get the boards I have with V6 130Ts to run at 300 MHz, I had to constrain each of the DSP48s, otherwise there was no chance.  This was based on the original verilog port, but I'm sure the problem with no pre-placement is the same.

Hi, thanks for your tips. I'm compiling the "X6000_ztex_comm4" project, which doesn't use any DSP48 block as I know. I also successfully compiled the same project on V6 130T device (with minor fix for MMCM, FIFO, JTAG core), just achieve at most 300MHz, same as yours, but no DSP48s. the compile time of V6 device is much less than spartan6 LX150. I guess the long-route resources of virtex6 make the difference.

next, I want to try difference implement options to go higher target, such as 350MHz.

BTW the power estimation given by ISE of V6 130T @ 300MHz is about 10W. below is the resource usage:

Code:
Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                85,173 out of 160,000   53%
    Number used as Flip Flops:              85,172
    Number used as Latches:                      1
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                     57,385 out of  80,000   71%
    Number used as logic:                   34,910 out of  80,000   43%
      Number using O6 output only:          14,978
      Number using O5 output only:             539
      Number using O5 and O6:               19,393
      Number used as ROM:                        0
    Number used as Memory:                   9,759 out of  27,840   35%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:         9,759
        Number using O6 output only:         9,759
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus: 12,716
      Number with same-slice register load: 12,452
      Number with same-slice carry load:       264
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                15,859 out of  20,000   79%
  Number of LUT Flip Flop pairs used:       62,383
    Number with an unused Flip Flop:         1,382 out of  62,383    2%
    Number with an unused LUT:               4,998 out of  62,383    8%
    Number of fully used LUT-FF pairs:      56,003 out of  62,383   89%
    Number of slice register sites lost
      to control set restrictions:               0 out of 160,000    0%
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Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 08/05/2013, 11:12:48 UTC
Quote
I'd like to ask what optimization options need to use to achieve > 190MHz clock speed? please help me, thanks very much.
The project won't "just compile" and achieve >190MHz.  Getting timing that high requires using Xilinx's SmartXplorer to brute force it.

Thanks for you hint. I've already tried SmartXplorer with default 7 built-in strategies, but can't achieve above 160MHz result. so, you mean I should use the cost table method to brute force it? thanks.
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Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
xbaby
on 07/05/2013, 06:07:36 UTC
I'm trying to compile the "projects/X6000_ztex_comm4" myself, for devices "xc6slx150, speed -3", under Xilinx ISE v13.4, and code from Github without any modification.

using default compiling option from "xilinx_fpgaminer.xise", under the goal of "Timing Performance", the placement failed. after change goal to "Minimum Runtime", the project compiled successfully, but the timing constrains can't be met. from the PAR report, the clock speed is only 153MHz (cycle 6.54ns). I'd like to ask what optimization options need to use to achieve > 190MHz clock speed? please help me, thanks very much.

Code:
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLK_100MHZ                  |     10.000ns|      9.689ns|     13.082ns|            0|          633|         1456|      3690036|
| TS_dynamic_clk_blk_clkfx      |      5.000ns|      6.541ns|          N/A|          633|            0|      3690036|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Slice Logic Utilization:
  Number of Slice Registers:                84,129 out of 184,304   45%
    Number used as Flip Flops:              84,129
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                     50,798 out of  92,152   55%
    Number used as logic:                   35,040 out of  92,152   38%
      Number using O6 output only:          15,507
      Number using O5 output only:             581
      Number using O5 and O6:               18,952
      Number used as ROM:                        0
    Number used as Memory:                   3,297 out of  21,680   15%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:         3,297
        Number using O6 output only:           449
        Number using O5 output only:             0
        Number using O5 and O6:              2,848
    Number used exclusively as route-thrus: 12,461
      Number with same-slice register load: 12,036
      Number with same-slice carry load:       425
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                15,049 out of  23,038   65%
  Nummber of MUXCYs used:                   22,144 out of  46,076   48%
  Number of LUT Flip Flop pairs used:       58,734
    Number with an unused Flip Flop:           959 out of  58,734    1%
    Number with an unused LUT:               7,936 out of  58,734   13%
    Number of fully used LUT-FF pairs:      49,839 out of  58,734   84%
    Number of slice register sites lost
      to control set restrictions:               0 out of 184,304    0%
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Topic
Board Group buys
Re: [Group Buy] Avalon ASICs CHIPS! Using JohnK as Escrow! Pledge reached!!
by
xbaby
on 23/04/2013, 00:07:16 UTC
Post
Topic
Board Group buys
Re: [Group Buy] Avalon ASICs CHIPS! 841 / 782.1 BTC Pledged!
by
xbaby
on 19/04/2013, 13:16:42 UTC
I'm in with 5BTC.

looking forward to this. thanks for helping.
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Topic
Board Hardware
Re: [ANN] Avalon ASIC chip distribution
by
xbaby
on 18/04/2013, 13:50:53 UTC
I'm in.

xbaby; 120; 10.32; 1xbbjJcbeD4Qi88QmJmMgTFSdm7b5WCG4

Thanks for you effort.
Post
Topic
Board Beginners & Help
Re: Hello trading itunes cards
by
xbaby
on 18/04/2013, 05:03:30 UTC
that's right. the currency is limited to same region.
Post
Topic
Board Beginners & Help
Re: How do you earn Bitcoins?
by
xbaby
on 18/04/2013, 04:32:02 UTC
you can try exchange for bitcoin by some ripple coin?
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Topic
Board Beginners & Help
Re: Is it all worth it?
by
xbaby
on 18/04/2013, 04:30:51 UTC
without a asic miner, it's totally worthless. please consider switching to LTC mining.
Post
Topic
Board Beginners & Help
Re: Introduce yourself :)
by
xbaby
on 18/04/2013, 04:29:33 UTC
ok. I'm a new comer for bitcoin. with some experience in hardware and PCB design.
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Topic
Board Beginners & Help
Re: a test and what time zone here?
by
xbaby
on 18/04/2013, 04:23:52 UTC
thanks for your information
Post
Topic
Board Beginners & Help
Topic OP
a test and what time zone here?
by
xbaby
on 18/04/2013, 02:39:36 UTC
a test and what time zone here?